Make:

  make is an application that is used to act as you specify on file
  dependencies.  Cryptic?  Read on.  As a programmer, you are constantly
  compiling and creating applications, etc.  The application may be the
  result of several pieces of source code.  Rather than manually retyping
  the compile commands for your code whenever you update a file, make
  lets you just type "make".

  make uses files called Makefiles to describe how the files in your project
  are related.  Lets imagine a software project with 3 pieces of source code:

    app.h   Header file
    main.c  Main
    sub.c   Function called by main

  Where their contents are as follows:

  app.h:
  #define VERSION 1
  extern void sub(void);

  main.c:
  #include <stdio.h>
  #include "app.h"

  int main(void)
  {
    printf("The current version is %d\n", VERSION);
    sub();
    return (0);
  }

  sub.c:
  #include "app.h"

  void sub(void)
  {
    printf("The current version is still %d\n", VERSION);
  }

  To compile these into an application, you would need to do the following:

    cc -c main.c
    cc -c sub.c
    cc -o app main.o sub.o

  Dependencies:

    Both main.c and sub.c depend upon app.h (since they both include
    it).  app depends upon main.o and sub.o (which in turn depend upon
    main.c and sub.c, respectively).  You could describe this set of
    dependencies as follows:

      app:
        main.o:
          main.c:
            app.h
        sub.o:
          sub.c:
            app.h

    In a Makefile, you would describe these dependencies in the following
    way:

    main.c sub.c: app.h
    main.o:       main.c
    sub.o:        sub.c
    app:          main.o sub.o

    Make decides that a file is out of date whenever a file that it
    depends upon is newer than it is.

    make looks at the file suffix (the part after the .) to decide
    what to do when a file is out of date.  For main.c and main.o,
    it has a built-in definition:

    .c.o:
          $(CC) -c $(<)

     where $(CC) is set to be the C compiler, and $(<) is the source
     file (main.c for example).

     At this point, we have described how the files depend upon each
     other, and (through makes built-in rules) we have told make how
     to regenerate .o files from .c files.

     The only thing left to describe is how to create app from main.o
     and sub.o.  This is done by modifying the above dependency description
     to add a rule (rules need to start with a TAB --- this can't be
     shown without messing up the layout, but there should be a TAB
     before each of the $(CC) rules in this file):

     app: main.o sub.o
            $(CC) -o app main.o sub.o

     We can also simplify our Makefile by removing the description of
     main.o depending on main.c (and sub.o depending on sub.c) --- as
     they are part of the default dependencies.

     In the end, your Makefile will look like (\t = TAB):

     main.c sub.c: app.h

     app: main.o sub.o
     \t$(CC) -o app main.o sub.o

     whenever you update a file, just type "make app" and it will
     recompile it.

     If you wish to only have to type "make", you must make the first
     rule the correct one.  This is usually accomplished by making a
     dummy "all" rule at the beginning:

     all: app
     main.c sub.c: app.h

     app: main.o sub.o
     \t$(CC) -o app main.o sub.o

Notes:

  For more on make, read the excellent O'Reilly book "Managing Projects
  with Make".